View M5M5V216ART-70HI_4694548.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
revision-03, 14.Jan.'03
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V216A is a f amily of low v oltage 2-Mbit static RAMs organized as 131,072-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.25m CMOS technology . The M5M5V216A is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5V216ATP, RT are packaged in a 44-pin 400mil thin small outline package. M5M5V216ATP (normal lead bend ty pe package) , M5M5V216ART (rev erse lead bend ty pe package) , both ty pes are v ery easy t o design a printed circuit board.
FEATURES
Single +2.7~+3.6V power supply Small stand-by current: 0.3A(3V,ty p.) No clocks, No ref resh Data retention supply v oltage=2.0V to 3.6V All inputs and outputs are TTL compatible. Easy memory expansion by S , BC1 and BC2 Common Data I/O Three-state outputs: OR-tie capability OE prev ents data contention in the I/O bus Process technology : 0.25m CMOS Package: 44 pin 400mil TSOP (II)
PART NAME TABLE
Version, Operating temperature Part name
Power Supply
Access time
Stand-by c urrent Icc(PD), Vcc=3.0V ty pical * 25C 40C
max. 55ns
M5M5V216ATP,RT -55HI I-version 2.7 ~ 3.6V -40 ~ +85C M5M5V216ATP,RT -70HI
0.3A 1A 70ns
Activ e current Ratings (max.) Icc1 (3.0V, ty p.) 25C 40C 70C 85C 45mA (10MHz) 1A 3A 8A 24A 5mA (1MHz)
* "ty pical" parameter is sampled, not 100% tested.
PIN CONFIGURATION
A4 A3 A2 A1 A0 S DQ1 DQ2 DQ3 DQ4 Vcc GND DQ5 DQ6 DQ7 DQ8 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BC2 BC1 DQ16 DQ15 DQ14 DQ13 GND Vcc DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC
A5 A6 A7 OE BC2 BC1 DQ16 DQ15 DQ14 DQ13 GND Vcc DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A4 A3 A2 A1 A0 S DQ1 DQ2 DQ3 DQ4 Vcc GND DQ5 DQ6 DQ7 DQ8 WE A16 A15 A14 A13 A12
Pin A0 ~ A16 S W OE BC1 BC2 Vcc GND
Function Address input Chip select input Write control input Output inable input Lower By te (DQ1 ~ 8) Upper By te(DQ9 ~ 16) Power supply Ground supply
DQ1 ~ DQ16 Data input / output
Outline: TP : 44P3W - H
RT : 44P3W - J
NC: No Connection
1
revision-03, 14.Jan.'03
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V216ATP,RT is organized as 131,072-words by 16-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully s t atic circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1 , BC2 , S , W and OE. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W ov erlaps with the low lev el BC1 and/or BC2 and the low lev el S. The address(A0~A16) must be set up bef ore the write cy c le and must be stable during the entire cy c le. A read operation is executed by s etting W at a high lev el and OE at a low lev el while BC1 and/or BC2 and S are in an activ e state(S=L). When setting BC1 at the high lev el and other pins are in an activ e stage , upper-by te are in a selesctable mode in which both reading and writing are enabled, and lower-by t e are in a non-selectable mode. And when setting BC2 at a high lev el and other pins are in an activ e stage, lowerby t e are in a selectable mode and upper-by te are in a non-selectable mode. When setting BC1 and BC2 at a high lev el or S at a high lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S. The power supply c urrent is reduced as low as 0.3A(25 C, ty pical), and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S BC1 BC2 W OE H L L L L L L L L X H L L L H H H L L L X H H H H L L L L L L X X L H H L H H L H H X X X L H X L H X L H Write Read Write Read Mode
Non selection Non selection
DQ1~8
DQ9~16
Icc
High-Z High-Z Standby High-Z High-Z Standby Din Dout High-Z High-Z Din Dout High-Z High-Z Din Dout Din Dout Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e
Write Read
High-Z High-Z
High-Z High-Z
BLOCK DIAGRAM
A0 A1
Note : "H" and "L" in this table mean VIH or VIL. L "X" in this table should be "H" or "L". L
High-Z High-Z
DQ 1
MEMORY ARRAY 131072 WORDS x 16 BITS A15 A16
CLOCK GENERATOR -
DQ 8
DQ 9
DQ 16
S BC1 BC2 W GND OE Vcc
2
revision-03, 14.Jan.'03
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply v oltage Input v oltage Output v oltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND With respect to GND With respect to GND Ta=25C I-v ersion (-HI) Ratings Units
Vcc VI VO Pd Ta T stg
-0.5* ~ +4.6 -0.5* ~ Vcc + 0.5 0 ~ Vcc 700 - 40 ~ +85 - 65 ~ +150
V mW C C
* -3.0V in case of AC (Pulse width < 30ns) =
DC ELECTRICAL CHARACTERISTICS
Symbol
( Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Conditions Min Ty p Max Vcc+0.3V Units
Parameter High-lev el input v oltage Low-lev el input v oltage
High-level output voltage 1 High-level output voltage 2
VIH VIL VOH1 VOH2 VOL II IO Icc1 Icc2
Low-lev el output v oltage Input leakage current Output leakage current Activ e supply c urrent ( AC,MOS lev el ) Activ e supply c urrent ( AC,TTL lev el ) Stand by s upply current ( AC,MOS lev el ) Stand by s upply current ( AC,TTL lev el )
IOH= -0.5mA IOH= -0.05mA IOL=2mA VI =0 ~ Vcc
BC1 and BC2=VIH or S=VIH or OE=VIH, VI/O=0 ~ Vcc
BC1 and BC2 < 0.2V , S< 0.2V = = > other inputs < 0.2V or = Vcc-0.2V = Output - open (duty 100%) BC1 and BC2=VIL , S=V IL other pins =V IH or VIL Output - open (duty 100%)
> < 1 > S = Vcc - 0.2V,other inputs = 0 ~ Vcc > < 2 > BC1 and BC2 = Vcc - 0.2V S < 0.2V Other inputs=0~Vcc =
2.0 -0.3 * 2.4
Vcc-0.5V
0.6 V 0.4 1 1
A
f = 10MHz f = 1MHz f = 10MHz f = 1MHz ~ +25C ~ +40C ~ +70C ~ +85C
-
45 5 45 5 0.3 1 -
60 15 60 15 2 5 10 30 0.5
mA
Icc3
A
Icc4
BC1 and BC2=VIH , S=VIL Other inputs= 0 ~ Vcc
or
S=VIH
mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for Vcc=3.0V and Ta=25C
* -3.0V in case of AC (Pulse width < 30ns) =
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions VI=GND, VI=25mVrms, f =1MHz VO=GND,VO=25mVrms, f =1MHz
(Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Ty p Max Units
Min
CI CO
8 10 pF
3
revision-03, 14.Jan.'03
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS
Supply v oltage Input pulse
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
2.7V~3.6V VIH=2.4V,VIL=0.4V Input rise time and f all time 5ns
Ref erence lev el
1TTL DQ CL
Including scope and jig capacitance
VOH=VOL=1.5V
Transition is measured 500mV f rom steady state voltage.(f or ten,t dis)
Output loads
Fig.1,CL=30pF CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits Symbol tCR Parameter Read cy cle time Address access time Chip select access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S high Output disable time af t er BC1 high Output disable time af t er BC2 high Output disable time af t er OE high Output enable time af ter S low Output enable time af ter BC1 low Output enable time af ter BC2 low Output enable time af ter OE low Data v alid time after address Min 55
55HI
Max 55 55 55 55 30 20 20 20 20 10 10 10 5 10 10 10 10 5 10 Min 70
70HI
Max 70 70 70 70 35 25 25 25 25
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ta(A) ta(S) ta(BC1) ta(BC2) ta(OE) tdis (S) tdis (BC1) tdis (BC2) tdis (OE) ten(S) ten(BC1) ten(BC2) ten(OE) tV(A)
(3) WRITE CYCLE
Limits Symbol Parameter Write cy cle time Write pulse width Address setup time
Address setup time with respect to W
55HI
Min 55 45 0 50 50 50 50 25 0 0 Max Min 70 55 0 65 65 65 65 30 0 0
70HI
Max
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S) tsu(D) th(D) trec(W) tdis (W) tdis (OE) ten(W) ten(OE)
By te control 1 setup time By te control 2 setup time Chip select setup time Data setup time Data hold time Write recov ery time Output disable time f rom W low Output disable time f rom OE high Output enable time f rom W high Output enable time f rom OE low
20 20 5 5 5 5
25 25
4
revision-03, 14.Jan.'03
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle
A0~16
tCR
ta(A) BC1
and / or
tv (A)
ta(BC1)
(Note3)
or
ta(BC2)
(Note3)
BC2
tdis (BC1) or tdis (BC1) ta(S)
S
(Note3)
tdis (S) ta (OE)
(Note3)
OE
(Note3) W = "H" lev el
ten (OE) ten (BC1) ten (BC2) ten (S)
tdis (OE)
(Note3)
DQ1~16
VALID DATA
Write cycle ( W control mode )
tCW A0~16 tsu (BC1) or tsu(BC2) BC1
and / or
BC2
(Note3)
tsu (S)
(Note3)
S
(Note3)
tsu (A-WH)
(Note3)
OE tsu (A) W tdis(OE) DQ1~16
DATA IN STABLE
tw (W) tdis (W)
trec (W)
ten(OE) ten (W)
tsu (D)
th (D)
5
revision-03, 14.Jan.'03
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC control mode)
tCW A0~16 tsu (A) BC1
and / or
tsu (BC1) or tsu (BC2)
trec (W)
BC2
S
(Note3) (Note5) (Note3)
W
(Note3)
(Note4) (Note3)
tsu (D) DQ1~16
DATA IN STABLE
th (D)
Write cycle (S control mode)
tCW A0~16
BC1
and / or
(Note4) (Note3)
BC2
tsu (A)
tsu (S)
trec (W)
(Note3)
S
(Note5)
W
(Note3)
(Note4)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S low , ov erlaps BC1 and/or BC2 low and W low. Note 5: When the f alling edge of W is simultaneously or priorto the f alling edge of BC1 and/or BC2 or the f alling edge of S, the outputs are maintained in the high impedance state. Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
6
revision-03, 14.Jan.'03
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol Vcc Parameter Limits Test conditions Min Ty p Max Units V V V
(PD) Power down supply voltage Byte control input BC1 & BC2
VI (BC) VI (S)
Chip select input S
Vcc=3.0V
~ +85C ~ +70C ~ +40C -40 ~ +25C
Icc
(PD)
Power down supply c urrent
1) S > Vcc - 0.2V = other inputs=0~Vcc 2) BC1 and BC2 > Vcc - 0.2V = S< 0.2V, other inputs=0~Vcc =
2.0 2.0 2.0 -
1 0.3
24 8 3 1
A A A A
Note 7: Typical parameter of Icc(PD) indicates the value for the center of distribution at 3.0V, and not 100% tested.
(2) TIMING REQUIREMINTS
Symbol Parameter Power down set up time Power down recov ery t ime Limits Test conditions Min Ty p Max Units ns ms
tsu (PD) trec (PD)
0 5
(3) TIMING DIAGRAM
BC control mode Vcc tsu (PD) BC1 BC2 2.2V BC1 , BC2 > Vcc - 0.2V = 2.7V 2.7V trec (PD) 2.2V
Note8: On the BC# control mode, the lev el of S# must be f ixed at S# > Vcc-0.2V or S# < 0.2V.
S control mode Vcc tsu (PD) 2.2V S S > Vcc - 0.2V = 2.7V 2.7V trec (PD) 2.2V
7
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

▲Up To Search▲

Price & Availability of M5M5V216ART-70HI

	To Download M5M5V216ART-70HI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .